Introduction of high tensile strain into Ge-on-Insulator structures by oxidation and annealing at high temperature

Abstract

It is demonstrated in this work that a high-temperature thermal process including oxidation and N2 annealing at 850 °C can provide a tensile strain of ∼0.58% at maximum into Ge-on-Insulator (GOI) structures without any special patterning or external stressors. The different impacts of oxidation and annealing on tensile strain generation, surface roughness, and crystal qualities in the GOI structures fabricated by Ge condensation and wafer bonding are systematically examined. A tensile strain of 0.47% is achieved without severe thermal damages under the optimal thermal process condition, which indicates the high potential of the present method for improving the performance of GOI n-channel metal-oxide-semiconductor field-effect transistors. The influence of thermal expansion mismatch between Ge and SiO2 is suggested as a possible physical origin of the high amount of tensile strain into GOI structures.