Abstract

The state of the art for electronic industries tends to offer products with smaller scales, lower cost, larger storage space, multi-functionality and low-power consumption. The latest package technology has advanced towards three-dimensional (3-D) system in package (SiP) design. However, reliability of interconnects becomes an important issue due to the complicated structure induced stress sensitivity for fractures. Therefore, optimizing the design is essential to improve reliability, especially for the delicate Through-Silicon Via (TSV) which is fabricated using high density interconnect technology.A 3-D TSV stacked-chips package model is constructed by finite element analysis (FEA) to investigate the thermo-mechanical behavior for packages stressed under temperature cycle test (TCT). The global/local method with convergence analyses are jointly applied and achieved an improvement of 74.4% in simulation efficiency. The viscoplastic solder joints, and the elastoplastic behavior with isotropic hardening for copper interconnects are considered in this FEA model, in which the maximum equivalent plastic strain is found to be located at the most critical copper bump and treated as an indicator for reliability. The significant factors, such as the CTE (coefficient of thermal expansion) of silicon substrate, silicon chip and TSV copper bump, are selected by using the fractional factorial design. copper; the thickness of silicon chip and the radius of TSV The objective function is constructed from the normalized regression model according to the response surface method. The results show that the optimal design performs a significant improvement by up to 43.416% for the reduced equivalent plastic strain after genetic algorithm (GA) optimization.To cope with design for manufacturability (DfM), the interval genetic algorithm (IGA) method is introduced for exploring the optimum interval range based on the defined objective error. Finally, the sensitivity analysis is conducted for each significant factor to determine the priority of accuracy control.

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