Internal and External Gettering of Iron Contamination in Power Technologies

Abstract

Substrate gettering and the contribution to the contamination reduction of backside layers are evaluated after high‐temperature annealing, following intentional iron contamination at the backside in silicon epitaxial wafers typical of power technologies. Iron is detected at the frontside by deep‐level transient spectroscopy within a depth corresponding to the actual devices. Herein, contamination occurring at the beginning of the semiconductor process flow is simulated and the role of the different gettering mechanisms is isolated. Substrate boron in epitaxial p over p+ wafers is effective in more than halving iron contamination at the front compared with a p‐only substrate, especially at high contamination doses. In the absence of a specific thermal cycle for oxygen precipitation and growth in the bulk, long thermal treatment at 1200 °C induces a significant precipitate growth even in the beginning of the process, greatly contributing to iron gettering in the bulk. However, this effect is found to strongly depend on the silicon condition after crystal growth. No significant contribution to iron gettering from a backside polycrystalline silicon layer is found after high‐temperature annealing, whereas a backoxide acts as diffusion barrier, effectively screening the substrate from contamination only for short thermal treatments or annealing temperature below 1000 °C.