Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Abstract

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical tight-binding (TB) calculations, this technique can be used to understand the dependence of the source-to-channel barrier height (Eb) and the active channel area (Saa) on three important parameters: (i) the gate bias (Vgs), (ii) the temperature, and (iii) the FinFET cross-section size. The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) Saa and (ii) |∂Eb/∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nanometer width limit. Furthermore, theoretical investigation of the spatial current density reveals volume inversion in thinner FinFETs near the threshold voltage.