Interconnect optimization to enhance the performance of subthreshold circuits

Abstract

Subthreshold circuits are shown to be the best candidate for satisfying the ultra-low power demand of battery-operated systems having moderate throughput. However, exponential increase in driver resistance in subthreshold region and increased global interconnect capacitance will become a major hurdle in improving the speed of subthreshold interconnects. Improving the speed of such low power circuits is a major design challenge in ultra low power domain. This paper presents a comprehensive analysis of Cu and mixed CNT bundle interconnects and investigates their performance in terms of delay and energy delay product (EDP) for future subthreshold circuits. This paper mainly contributes towards optimizing the geometrical (aspect ratio scaling) and process parameters of interconnects especially for subthreshold circuits to increase their speed. Crosstalk analysis has also been carried out with the proposed interconnect geometrical parameters. It has been found that aspect ratio scaling significantly reduces the interconnect delay and switching energy and at minimum aspect ratio, Cu wire performs better than even an optimized mixed CNT bundle for global interconnect length under subthreshold conditions.