Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs

Abstract

In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.