Integrated experimental and computational approach for residual stress investigation near through-silicon vias

Abstract

The performance of three-dimensional integrated circuits is decisively influenced by the thermo-mechanical behavior of through-silicon vias (TSVs), which are subjected to stresses formed during fabrication process as well as cyclic operation as a result of coefficients of thermal expansion (CTEs) mismatch between the silicon substrate, passivation layers, and metallic conduction paths. In this work, we adopted an integrated approach combining micro-Raman, wafer curvature experiments, and finite element (FE) modeling to study the triaxial residual stresses in silicon in the vicinity of W-coated hollow TSVs. A comparison of the experimental and calculated Raman shifts from a TSV cross section allowed a validation of the FE model, which was then extended to a non-sliced TSV. In the next step, the calculated bulk strains were compared with the ones measured using synchrotron X-ray micro-diffraction in order to specifically assess the stress decrease in Si as a function of the distance from the TSV wall within ∼25 μm. The experimental verification of the FE model demonstrates the importance of combined experimental-computational approaches to study stresses in micro-scale devices with complex morphology.