Initial thermal stress and strain effects on thermal mechanical stability of through silicon via

Abstract

This paper is concerned with the thermal mechanical stability of 3D TSV with initial thermal stress and deformation during working stage. Different from the previous results, integrated circuits (IC) packaging and fabricating process (PFP) is considered to obtain the initial thermal stress and strain for working stage. During the PFP of IC, the through silicon via (TSV) may go through several different processes, such as, making redistribution layer (RDL), reflow soldering, and filling under-fill. Since more than 70% of the PFP brings high thermal load, plastic deformation on TSV Cu is inevitable during PFP. The accumulation of the plastic deformation leads to thermal residual stress and strain at the beginning of working cycling stage. The thermal mechanical reliability and mechanism of the TSV were investigated by finite element (FE) method. The influence of thermal residual stress on the IC fatigue life was studied by comparing neglecting PFP (NPP) model with considering PFP (CPP) model. With different forms of plastic deformation and effective plastic strain accumulation during PFP, the lifetime is shortened at the middle part and prolonged in the TSV Cu interfacial line. The precision of evaluation and prediction the IC reliability was improved by CPP greatly, e.g. the minimal fatigue life of the TSV unit is 75cycles for NPP and 118cycles for CPP. With full consideration of the thermal mechanical mechanism related to the IC PFP, the fatigue life will be prolonged.