Abstract
In this paper, the InGaAs junctionless (JL) FinFET with notable electrical performance is demonstrated. The device with $W_{\mathrm{ fin}}$ down to 20 nm, EOT of 2.1 nm, and $L_{G} = 60$ nm shows high $I_{\mathrm{ ON}} = 188~\mu \text{A}/\mu \text{m}$ at $V_{DD} = 0.5$ V and $I_{\mathrm{ OFF}} = 100$ nA/ $\mu \text{m}$ , $I_{\mathrm{ ON}}/I_{\mathrm{ OFF}} = 5 \times 10^{5}$ , DIBL = 106 mV/V and SS = 96 mV/dec. The device also exhibits a decent extrinsic transconductance ( $G_{\mathrm{ m}}$ ) of 1142 $\mu \text{S}/\mu \text{m}$ at $V_{\mathrm{ DS}}$ of 0.5 V. This high performance is attributed to the moderate doping concentration to ensure the channel carriers could be effectively depleted and the low $R_{\mathrm{ SD}}$ realized by self-aligned Ni-InGaAs alloy S/D. Furthermore, we also examine the temperature dependence of the main electrical parameters of the JL transistor.
Highlights
As the CMOS devices keep scaling to the sub-10 nm technology nodes and beyond, suppressing short channel effects (SCEs) has become stringent and a critical challenge because of decreasing gate controllability
The device has a high ION of 188 μA/μm at VDD = 0.5 V and IOFF = 100 nA/μm; these data were normalized by the total effective channel width Wtot = (No of fin) × (2 × Hfin + Wfin) and ignored the effect of substrate leakage current
The capacitance equivalent thickness (CET) is 2.1 nm, and the minimum Dit value extracted by the conductance method is approximately 1.6 × 1012 cm−2 · eV−1 at the trap energy level of 0.5 eV above valence band (EV) (see the Fig. 4(b))
Summary
As the CMOS devices keep scaling to the sub-10 nm technology nodes and beyond, suppressing short channel effects (SCEs) has become stringent and a critical challenge because of decreasing gate controllability. INDEX TERMS Junctionless (JL) transistor, InGaAs nMOSFETs, FinFET, high-k dielectric, Ni-InGaAs, metal source/drain.
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