Influence of the Gate Height Engineering on the Intrinsic Parameters of UDG-MOSFETs With Nonquasi Static Effect

Abstract

This paper presents the results of a systematic theoretical investigation on the impact of gate height on the analog and radio-frequency (RF) performances of underlap-FinFET devices. The conventional underlap-FinFETs offer lower on current $(I_{\rm on} )$ and higher distributed channel resistance $(R_{\rm ch} )$ . This paper shows that a higher gate height improves both $I_{\rm on} $ and $R_{\rm ch} $ due to higher gate side-wall fringing fields. In this paper, the various figure of merits (FOMs) for analog applications of the underlap-FinFETs such as drain current $(I_{\rm ds} )$ , transconductance $(g_{m} )$ , transconductance generation factor $(g_{m} /I_{\rm ds} )$ , output resistance $(R_{o} )$ , and intrinsic gain $(g_{m} R_{o} )$ are systematically analyzed for different values of gate height and reported. The RF FOMs studied include intrinsic capacitances $(C_{\rm gs} , C_{\rm gd} )$ and resistances $(R_{\rm gs} , R_{\rm gd} )$ , transport delay $(\tau _{m} )$ , cutoff frequency $(\,f_{T} )$ , and the transit frequency of maximum available power gain $(\,f_{\rm MAX} )$ . This paper clearly demonstrates that the gate height is a critical technology parameter in improving the analog performance of underlap-FinFETs.