Abstract
The top side interconnection of a power semiconductor by aluminum heavy wire bonds is one key point of failure during operation. State of the art lifetime models mostly focus on the operating conditions of the power module. They can be used to correlate lifetime testing data with application conditions but cannot cover the wide range of design parameters relevant for the development of a power module. An extensive power cycling study was conducted in order to evaluate the additional stress induced in the bond interface on the chip by the wire bond loop, with the main focus being on the load current in the wire bond. A strong correlation between the power loss density in the bond loop and the tested lifetime was found over a wide range of load currents. Additional influence factors, such as the number of stitches, were identified in this study. This data can be used to expand existing lifetime models and make them more relevant for power module design.
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