A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs

Abstract

A self-regulating negative charge pump using eight-phase clock for the input buffer application with a wide range of load current is presented in this paper. The eight-phase clock generated by delay-locked loop is adopted to reduce the area of the decoupling capacitance tremendously. Zero reversion loss cross-coupled topology is used to eliminate reversion loss, thus improving energy efficiency. Furthermore, the self-regulating system is proposed to adjust the driving capacity of the negative charge pump according to the load current of the input buffer, making the output of the charge pump stable for a wide range of load current. This design is implemented in 65nm CMOS process. According to the results, the decoupling capacitance can be reduced by 95.6%. The output voltage stays stable around -380mV with the load current from 40mA to 70mA.