Abstract
In this paper a ZrO2/SiO2/4H‐SiC dielectric system for potential application as gate dielectric for SiC MOSFETs is investigated. An enhanced breakdown performance for this type of dielectric stacks having typical value of critical field of 17 MV cm−1 and reaching a maximum value of 20 MV cm−1 is presented. The observed results are explained based on high‐k layer properties in conjunction with a reduced impact ionization effect in SiO2 layer. Electrical and structural properties of this dielectric stack are measured and analyzed. Growth temperature of atomic layer deposition process seems to be a crucial parameter that influences on layer microstructure and electrical properties such as permittivity of high‐κ layer and critical electric field for all dielectric stacks.
Published Version
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