In situ Formation of HfN/HfSiON Gate Stacks with 0.5 nm Equivalent Oxide Thickness Utilizing Electron Cyclotron Resonance Plasma Sputtering on Three-Dimensional Si Structures

Abstract

In situ formation of HfN/HfSiON gate stacks on three-dimensional (3D) Si structures using electron cyclotron resonance (ECR) plasma sputtering method was investigated. The conditions of postdeposition annealing (PDA) of in situ formed HfN/HfSiON were optimized to suppress reactions occurring at the interfaces of the gate stack structures for realizing a small equivalent oxide thickness (EOT), low leakage current, and a low density of interface state (Dit). It was found that 600 °C/15 s was a suitable condition of PDA of the HfN/HfSiON/p-Si(100) structure to decrease Dit and hysteresis width in the capacitance–voltage (C–V) characteristic. The EOT and Dit of HfN/HfSiON/p-Si(100) annealed at 600 °C were 0.5 nm and an order of 1011 cm-2 eV-1, respectively. Furthermore, an excellent C–V characteristic of the HfN/HfSiON gate stack annealed at 600 °C was obtained even on 3D Si structures, and the EOT was as small as 0.53 nm.