In-Plane Solid-Liquid-Solid Growth and Engineering of Si and Si/Ge Nanowires for Integratable High Performance Fin-like Thin Film Transistors

Abstract

Self-assembly growth of quasi-1D nanowires (NWs) has been a popular, high yield and low cost technology to fabricate ideal semiconducting channels for fin-like field effect transistors or thin film transistors (TFTs). However, a technical challenge to implementing this approach for large scale electronic applications arises from the fundamental difficulty in collecting and positioning these tiny 1D building blocks into precise locations for convenient electric connection and integration. This is particularly true when the SiNWs were grown with gas-feeding vapor-liquid-solid (VLS) approach, where the as-produced SiNWs are typically standing ones on substrate, and thus require further delicate manipulations to arrange them on planar architecture. Fortunately, this challenge can be addressed by adopting a self-assembly in-plane solid-liquid-solid (IPSLS) growth of Si nanowires (SiNWs), where a thin film of amorphous Si (a-Si) is fed as precursor layer to drive the indium (In) or tin (Sn) nano-droplets to move and produce well-defined crystalline SiNWs behind.[1] Remarkably, a precise control of the location, the growth routine and the geometry of the SiNW channels can be accomplished via a simple low temperature (<350 oC) process in conventional plasma enhanced chemical vapor deposition (PECVD) system. We will first demonstrate a reliable batch-manufacturing of parallel SiNW arrays upon glass substrates, which can serve as high mobility channels in fin-like thin film transistors (Fin-TFTs) for large area display application. Specifically, the SiNWs Fin-FETs achieve a high hole mobility of >150 cm2V–1s–1, on/off ratio >106 and excellent subthreshold swing of 120 mV/dec. In addition, the tiny SiNWs, of ~60 nm in diameter and 2 μm apart grown on glass substrate, are transparent to visible light.[2] Furthermore, we will show that the geometry degree of freedom can also be programmed during the in-plane growth of SiNWs.[3,4,5] Finally, an alloy mixture or amorphous bilayer feeding control will be presented, which can help to achieve a self-automated phase-separation and diameter modulation in a unique Si/Ge superlattice nanowire structure. There results could indicate a promising strategy to tailor the Si or SiGe nanowires for high perfomance large area electronics.