Deterministic deployment of in-plane silicon nanowires for high performance large area electronics

Abstract

One-dimensional (1D) nanostructures, such as semiconductor nanowires (NWs), nanobelts (NBs), and carbon nanotubes (CNTs), could be of ideal building blocks for electronic devices and might extend the remarkably successful scaling of microelectronics industry [3–6]. While the benefits of fin-gate field effective transistors (FET) have been very well established and implemented in micro-electronics, the same quasi-1D nano channel (diameter $\lt100$ nm) technology is hard to apply in large area electronics where the resolution of lithography is only 2 or 3 um. Self-assembly growth mediated by nano metal droplets can offer a low cost and high throughput solution to manufacture of tiny crystalline silicon nanowires (SiNWs). However, a precise location and orientation control of the self-assembly SiNWs over large area are still difficult to achieve with the common vapor-liquid-solid (VLS) growth mechanism. In this work, we will introduce a new in-plane solid-liquid-solid (IPSLS) growth, [1] which enables a precise growth routine and geometry controls over the self-assembly SiNWs. During an IPSLS growth, an amorphous Si (a-Si) thin film is used as the precursor layer that is absorbed by nano droplets of indium (In) to move laterally and produce continuous crystalline SiNWs behind. This growth can be activated at a rather low temperature $\lt 350$ °C in conventional PECVD system. Based on this unique capability, orderly crystalline SiNW channels can be easily manufactured over glass substrate, providing a key basis to fabricate high mobility fin-like thin film transistors (TFTs) for large area and high resolution display. Initial integration of the in-plane SiNWs for Fin-FETs has demonstrated a high hole mobility of $\gt150$ cm2V–1s–1, high on/off ratio $\gt 10^{6}$ and excellent subthreshold swing of only 120 mV/dec, via a low temperature procedure fully compatible to a-Si TFT technology. More importantly, thanks to a precise position and compositional controls over the tiny SiNWs [2–6], primitive logics can be constructed over the SiNW channels. Finally, a programmable geometry and line-shape engineering of the in-plane SiNWs will be showcased, which enables a reliable and low-cost fabrication of highly stretchable c-Si nano springs for high performance flexible and stretchable electronics. The SiNW logic device performance and the key control parameters of this IPSLS growth strategy, as well as its unique potentials in advanced 3D microelectronics, will be addressed.