Abstract
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.
Highlights
The latency of dynamic random access memory (DRAM) has been a critical issue for two primary reasons [1]
We have proposed two new in-DRAM cache management techniques
Despite the recent introduction of various in-DRAM cache architectures, there was a lack of interest in how to manage them
Summary
The latency of dynamic random access memory (DRAM) has been a critical issue for two primary reasons [1]. Russell et al proved that the instructions per cycle of the applications dealing with big data could be significantly improved by reducing the DRAM latency [8]. In order to reduce the sensing and pre-charge time, for example, the number of cells connected per bit-line should be reduced [18]. This leads to an increase in the number of bit-line sense amplifiers, and increases the chip size Timing constraints, such as CAS latency (tCL) are mainly influenced by the speed of the data path. In order to improve this speed, the capacitive metal loading of the data path signal should be decreased, or its driver strength should be increased These approaches may increase the cost or power consumption. We focus on the in-DRAM cache among various skills to reduce the latency of DRAM, and discuss its management method
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