Improving the Reliability of TMR With Nontriplicated I/O on SRAM FPGAs

Abstract

Triple modular redundancy (TMR) with repair is a commonly employed mitigation strategy used on SRAM field-programmable gate arrays (FPGAs) to reduce the effects of ionizing radiation and improve a circuit’s sensitive cross section. This article examines TMR circuits, where the I/O ports of the circuit have not been triplicated, but the internal circuitry has. Such circuits introduce single-point failures (SPFs) into the circuit that limit the neutron cross-sectional improvement offered by TMR to only $3\times $ for the b13 benchmark circuit used in this article. This article proposes two different mitigation techniques to address SPFs, which alter the placement and routing of the circuit. These mitigation techniques reduce the neutron cross section by $26\times $ over the unmitigated circuit while minimally affecting the circuit’s maximum clock frequency and resource utilization.