Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs

Abstract

In this brief, we explore the electrostatics of junctionless accumulation mode (JAM) device with asymmetric spacers to improve the device performance parameters at 20nm technology node. Dual-kS JAM device is designed and analysed using source side dual-k and drain side low-k spacers. Dual-kS JAM structure shows unequal current at positive and negative drain biases with different device electrostatics. Selective length of the dual-k spacer on the source side of Dual-kS device can reduce the intrinsic delay by 25.3% with reduced short-channel effects in comparison to the Low-k spacer device. Proposed 6T SRAM cell using Low-k and Dual-kS devices shows improvement in read SNM by 9.7%, write margin by 3.8%, read delay by 3.8%, write delay by 20.3% with 25% reduction in leakage power in comparison to Low-k SRAM cell without area overhead. It is observed that proposed SRAM cells show improved performance metrics compared with the Low-k JAM and the inversion mode based SRAM cells even at lower supply voltages.