Asymmetric Junctionless Transistor

Abstract

In this chapter, an asymmetric gate sidewall spacer junctionless transistor (JLT) is used to improve the SRAM performance metrics. Asymmetric JLT (known as dual-kS JLT) is designed using dual-k and low-k spacer at source side and drain side, respectively. Asymmetric JLT structure designed using drain-side dual-k spacers and source side low-k spacer is known as dual-kD JLT. Dual-kS JLT structure converts into dual-kD JLT by simply changing polarity of source and drain terminals. The conflict between the size of access transistor and pull-up/pull-down transistors makes the design of SRAM challenging at scaled dimensions and lower supply voltages. The proposed dual-kS JLT fulfills the contrasting requirement of size of access transistor in SRAM cell and leads to improved performance at lower supply voltages. Proposed SRAM cell using asymmetric JLTs shows improvement in hold margin by 7.6%, read margin by 7.4%, read delay by 41.6%, and write delay by 25% with same write noise margin in comparison to the conventional SRAM cell. This study shows that device-circuit co-design approach can address the challenges of futuristic SRAM cells at scaled gate lengths.