Improving IEEE 1588v2 clock performance through controlled packet departures

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Packet delay variation (PDV) is the dominant impairment in packet-based synchronization systems. One way to mitigate its effect is to apply advanced filtering techniques on phase error information derived from packet arrival events. In this letter we consider an alternative approach in which the backpressure to the background traffic source is coordinated with timing packet generation such that the PDV is completely eliminated. Although the proposed method is limited to tree network topologies, the results are notable due to complete elimination of the PDV noise even if the background traffic load approaches 100%.