Improving Accuracy, Area and Speed of Approximate Floating-Point Multiplication Using Carry Prediction

Abstract

The arithmetic units are the most essential in digital circuits’ construct, and the enhancement of their operation would optimize the whole digital system. Among them, multipliers are the most important operational units, used in a wide range of digital systems such as telecommunication signal processing, embedded systems and mobile. The main drawback of a multiplication unit is its high computational load, which leads to considerable power consumption and silicon area. This also reduces the speed that negatively affects the digital host functionality. Estimating arithmetic is a new branch of computer arithmetic implemented by discarding or manipulating a portion of arithmetic circuits and/or intermediate computations. Applying estimated arithmetic in arithmetic units would improve the speed, power consumption and the implementation area by sacrificing a slight amount of result accuracy. An estimated truncated floating-point multiplier for single precision operands which is capable of compensating the errors to a desired level by applying the least significant columns of the partial product matrix is developed and analyzed in this article. These errors are caused by removing a number of carry digits in the partial product matrix that have a direct contribution in rounding the floating-point numbers. The evaluation results indicate that the proposed method improves speed, accuracy and silicon area in comparison to those of the common truncated multiplication methods.