Improvement on Address Discharge Characteristics for Overall Subfield Time Using Additional Scan Voltage in AC PDP

Abstract

The address discharge time lags are investigated in each subfield time in AC PDP and shortened by changes in the amplitude of the additional scan voltage during total subfield time under the stable address voltage margin range. During the reset period, the reset discharge is produced by applying the high positive-going ramp voltage and the wall charge in a cell is generated. That wall charge plus the external address voltage induce the address discharge. In the first subfield time, the address discharge is fast produced than the other subfield times because the wall charge are much remained by the high positive-going ramp voltage during the reset period. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the modified driving method to shorten the total address discharge time is proposed by applying the different additional scan voltages in each the subfield time.