Improvement in Fermi-Level Pinning of p-MOS Metal Gate Electrodes on HfSiON by Employing Ru Gate Electrodes

Abstract

Methods of improving Fermi-level pinning of pure metal gate electrodes on Hf-based high-k dielectrics have been investigated. The pinning phenomenon is a crucial problem, resulting in an unintentional threshold voltage increase in p-MOSFETs when applying pure metal gate electrodes such as Ru and TiN in Hf-based high-k CMOS. After systematic investigation of the relation between oxygen vacancies in Hf-based high-k dielectrics and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. It is necessary to modulate the stable pinning energy position of Hf-based high-k dielectrics in p-MOSFETs in order to obtain thin EOTs in the gate-first process.