Interface engineering and chemistry of Hf-based high-k dielectrics on III–V substrates

Abstract

Recently, III–V materials have been extensively studied as potential candidates for post-Si complementary metal-oxide-semiconductor (CMOS) channel materials. The main obstacle to implement III–V compound semiconductors for CMOS applications is the lack of high quality and thermodynamically stable insulators with low interface trap densities. Due to their excellent thermal stability and relatively high dielectric constants, Hf-based high-k gate dielectrics have been recently highlighted as the most promising high-k dielectrics for III–V-based devices. This paper provides an overview of interface engineering and chemistry of Hf-based high-k dielectrics on III–V substrates. We begin with a survey of methods developed for generating Hf-based high-k gate dielectrics. To address the impact of these hafnium based materials, their interfaces with GaAs as well as a variety of semiconductors are discussed. After that, the integration issues are highlighted, including the development of high-k deposition without Fermi level pinning, surface passivation and interface state, and integration of novel device structure with Si technology. Finally, we conclude this review with the perspectives and outlook on the future developments in this area. This review explores the possible influences of research breakthroughs of Hf-based gate dielectrics on the current and future applications for nano-MOSFET devices.