Abstract
Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.
Highlights
To keep the communication between Internet of Things (IOT) devices secure, the data often require encryption before being transmitted [1], and true random number generators (TRNGs) are indispensable primary components in many encryption algorithms [2,3]
Cell to enhance inherent noise sensitivity. Throughput is another obstacle for utilizing Static random-access memory (SRAM) as a TRNG because the power-down time between two power-on cycles must be long enough to avoid the degradation of the randomness of power-on values by the remaining charge
A novel SRAM-based TRNG is proposed; its implementation consists of two phases: irradiation exposure with zero voltage bias and hardware postprocessing
Summary
To keep the communication between Internet of Things (IOT) devices secure, the data often require encryption before being transmitted [1], and true random number generators (TRNGs) are indispensable primary components in many encryption algorithms [2,3]. IOT applications (e.g., smart home, wireless sensor networks, and even smart city), the secure data transmission become more and more of a concern [13] These IOT devices are usually source-constrained and lack dedicated hardware security components such as TRNGs, which leads to poorly encrypted communication, or often no encryption at all. A higher min-entropy indicates that SRAM power-on values will be more random and can provide a great entropy source for the construction of a TRNG [21]. The power-on values of such cells are easy to flip between any two power-on measurements due to inevitable environmental noise These noisy cells increase the entropy of the power-on sequence and provide a superb source of randomness, making it possible to utilize SRAM as a TRNG [19]
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