Multilayer Secure Hardware Network Stack using FPGA

Abstract

This paper presents an implementation of a User Datagram Protocol (UDP)/Internet Protocol (IP) Hardware network Stack using Field Programmable Gate Array (FPGA) [1] and technology to secure and protect data integrity and authenticity at three layers: Transport Layer, Network Layer and Data Link layer using True Random Number Generator (TRNG) digital signal processor (DSP) intellectual property (IP) Core [4]. UDP/IP stack is preferred proposal over Transport Control Protocol (TCP)/Internet Protocol (IP) stack as it is connectionless oriented, and widely used in Internet of Things (IoT), Industrial IoT (IIoT), Virtual Protocol Network (VPN), Video Conference, Voice over Internet Protocol (VoIP), Avionics and defense communication systems. Due to its technology independent, digital entropy source, easy to integrate and port to FPGA, TRNG is preferred over other reported cost-effective security methods like Static Random Access Memory (SRAM) based Physical Un-clonable Functions (PUF) generates random number based on start up behavior due to nano variations in circuit elements in addressing cloning, impersonation and data integrity loss, and also TRNG is not effected by environmental fluctuations such as voltage, temperature, and noise. However, cross inverters in SRAM PUF can be used as source of entropy in TRNG. FPGA based Hardware network stack is preferred over software network stack as it reduces the execution overhead in the Operating System (OS), Hardware network stack node is independent of Microprocessors as it consists of its own Digital Clock Manager (DCM), Memory Blocks, Dedicated Hardware Interfaces, and System on Chip (SoC) IP Cores which are configurable and extendable based on requirements. Hardware based network stack is susceptible to loss of data integrity and authenticity due to 1. Unstable digital circuits, 2. Noise diode and register, small AC voltage, polarity semiconductor, 3. instability of oscillator (jitter in circuits), 4. Meta-stability of flip-flops, 5. Cross inverters in SRAM circuits (SRAM PUF) and 6. Block RAM write conflict [7]. Multilayer secure Hardware network node is important as the data integrity and authenticity is responsible for good communication network with the high performance and throughput. This paper discusses about, how TRNG DSP IP Core is used in securing the three layers of the FPGA based UDP/IP Hardware Network Stack to secure data.