Improved device performance by multistep or carbon co-implants

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High-energy ion implantation is used for forming the collector in vertical bipolar transistors in a BiCMOS process. Secondary defects, remaining after annealing the implant damage, give rise to an increased leakage current and to collector-emitter shorts. These shorts reduce the transistor yield. The use of multiple step implants or the introduction of a C gettering layer are demonstrated to avoid dislocation formation. Experimental results show that these schemes subsequently lower the leakage current and dramatically increase device yield. The presence of C can cause increased collector/substrate leakage, indicating that the C profile needs to be optimized with respect to the doping profiles. >