Improved Design of C2PL 3‐2 Compressors for Inner Product Processing

Chua-Chin Wang,Chenn-Jung Huang,Po-Ming Lee

doi:10.1080/10655140290011195

Abstract

The inner product of two vectors might be one of the most frequently used mathematical operations in digital computation. The design style of inner product processor will become a critical issue of performance. So does its basic building block, i.e. 3‐2 compressor. In this work, improved designs of 3‐2 C2PL‐based compressors are presented which can be used to build a fast inner product processor. The features of our compressors include a short delay minimized by HSPICE optimization, less transistor count, and high fan‐out.

Highlights

In digital computation, the inner product of two vectors might be one of the most frequently used mathematical operations [1]
Many high-speed logic design styles have been announced to resolve the propagation delay caused by inner product
Domino logic [2] cannot be non-inverting; NORA [3] has the charge sharing problem; all-N-logic [4] and robust single phase clocking [5] cannot operate correctly under clocks with short rise time or fall time, which cannot be integrated with other part of logic design; single-phase logic [6] and Zipper CMOS [7] contain slow P-logic blocks

Summary

INTRODUCTION

The inner product of two vectors might be one of the most frequently used mathematical operations [1]. Many high-speed logic design styles have been announced to resolve the propagation delay caused by inner product. According to the analysis of Zhang’s 3-2 compressor, Zhang’s original design is verified to possess poor fan-out. To overcome this shortage, the output buffers are re-tuned to make the compressor have an enhanced fan-out capability.

3-2 Compressor II

CONCLUSION