Implementation of optimized vedic multiplier using CMOS technology

Abstract

This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.