Design of Power Efficient Vedic Multiplier using Adiabatic Logic

Abstract

Various “arithmetic operations”, “signal and image processing systems” and “communication devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient mathematical system which focuses on solving tedious problems using 16 Vedic Sutras in a simpler and faster manner. The evolution of technology demands for “low power design” in the domain of integrated circuit. This led to the invention of varied adiabatic logic for low power operations. The uniqueness of Vedic mathematics and adiabatic logic is combined to design high speed and power-efficient multipliers. In this paper, a new adiabatic logic “Complementary Pass Transistor Adiabatic Logic” (CPAL) is used to design 8-bit Vedic multiplier. To authenticate the superiority of the proposed design, comparative performance analysis is carried out with respect to CMOS and other adiabatic logics like 2N-2N2P and “Efficient Charge Recovery Logic” (ECRL) based on 150nm technology. The simulation has been accomplished by the use of TANNER SPICE 16 tool. Simulation result validates the reduction of Power Delay Product (PDP) of the proposed CPAL Vedic multiplier design in comparison to the aforementioned techniques. The proposed technology offers a power-efficient solution for modern designs.