Abstract
The authors describe the implementation of an ATM (asynchronous transfer mode) switching element with 16 inputs and 16 outputs at 600 Mb/s each. The single-board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element has become feasible using advanced (Bi)CMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queuing memory is treated in detail. A comparison between memory pooling and individual output queues is presented. By choosing the latter solution, the development schedule could be kept very tight. The testability of the chips remains good despite the high gate complexity. It is also shown that integrated TDM (time-division multiplexing) buses should be preferred over external switching means, e.g., a ring topology. >
Published Version
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