The interconnection network using the ATM switch for message-based multiprocessor systems

Abstract

In a message-based multiprocessor system that consists of message-communicating processors, the interconnection network is really a crucial part for fast processor communication. Among various interconnection methods, using the high-speed asynchronous transfer mode (ATM) switch is an attractive approach to constructing large-scale multiprocessor systems with low latency and high throughput. The interconnection network for fast processor communication is proposed in this paper. For the efficient use of the ATM switch, a group of the cell interface modules (CIMs) called a cell router which performs cell multiplexing and demultiplexing, is located between the processor groups and the ATM switch. In this proposed system, an expanded internal cell format in which three bytes are added for the switch routing information, is used. The interconnection network uses three routing strategies: the ATM switch routing using the switch routing information, the cell router routing using the virtual path identifier (VPI), and the cell reassembly routing using the virtual channel identifier (VCI). The interconnection network consists of a N/spl times/N folded switch and N cell routers. Since each cell router has M processor interfaces, the maximum N/spl times/M processors can be interconnected. In terms of message-passing latency and scalability, the interconnection network using the ATM switch shows a significant improvement on the performance. The transmission overhead of the interconnection network using the ATM switch has also been evaluated. The overhead ratio of the message communication using ATM switch is almost 15%.