Impacts of plasma process-induced damage on MOSFET parameter variability and reliability

Abstract

Plasma process-Induced Damage (PID) is one of the critical issues in designing Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs), because PID is believed to enhance reliability degradation and the variability. This paper presents how PID impacts on the variability and reliability characterization by focusing on two key damage creation mechanisms, i.e., Plasma-induced Physical Damage (PPD) and Charging Damage (PCD). In PPD mechanisms, the effects of Si loss in the source/drain extension region and latent defects on MOSFET performance are discussed by means of the PPD range theory and Technology-Computer-Aided-Design (TCAD) simulations. It is presented that, under the fluctuation of plasma parameters, PPD enhances variability of threshold voltage shift (ΔVth) and drain current. Regarding PCD mechanisms, ΔVth variation due to high-k dielectric damage is investigated by reviewing an antenna ratio distribution reported so far. Finally, two key concerns are discussed as future perspective—PPD on a fin-structured FET and PCD on high-k Time-Dependent Dielectric Breakdown (TDDB) characterization. Since PID is the intrinsic nature of plasma processing, variability enhancement and reliability degradation by PID should be taken into account for future Very-Large-Integration (VLSI) circuit designs.