Modeling of defect generation during plasma etching and its impact on electronic device performance—plasma-induced damage

Abstract

The increasing demand for the higher performance of ultra-large-scale integration (ULSI) circuits requires the aggressive shrinkage of device feature sizes in accordance with the scaling law. Plasma processing plays an important role in achieving fine patterns with anisotropic features in metal–oxide–semiconductor field-effect transistors (MOSFETs). This article comprehensively addresses the negative aspects of plasma processing, i.e. plasma process-induced damage, in particular, the defect creation induced by ion bombardment in Si substrates during plasma etching. The ion bombardment damage forms a surface modified region and creates localized defect structures. Modeling and characterization techniques of the ion bombardment damage in Si substrates are overviewed. The thickness of the modified region, i.e. the damaged layer, is modeled by a modified range theory and the density of defects is characterized by photoreflectance spectroscopy (PRS) and the capacitance–voltage technique. The effects of plasma-induced damage (PID) on MOSFET performance are presented. In addition, some of the emerging topics—the enhanced parameter variability in ULSI circuits and recovery of the damage—are discussed as future perspectives.