Impact of varying channel length on Analog/RF performances in a novel n-type silicon-based DG-JLT

Abstract

Shrinking MOSFETs suffer performance hits due to short-channel effects and leakage. Junctionless transistors JLTs emerge as promising alternatives due to simpler fabrication and better gate control. This paper investigates the analog and RF performance characteristics of n-type Silicon-Based Double Gate Junctionless Transistors with varying channel lengths (15 nm, 20 nm, and 25 nm) This study evaluates analog device performance through critical parameters: drain current density (Id), transconductance (gm), output resistance (RO), intrinsic gain (gmRO), and transconductance generation factor (gm/Id). These parameters assess current handling, gain characteristics, and design efficiency, providing a comprehensive analysis for analog circuit applications. Results indicate that the device having 15 nm channel length exhibits a transconductance which is 25.38 % more than the 20 nm variant and drain current which is 44.7 % more than the latter, suggesting its superior performance to devices with longer channel lengths. In addition, the RF performance of the devices is evaluated using the small signal model of the device. This work further investigates the high-frequency response of the devices using key figures of merit (FoMs): gate capacitances (Cgs, Cgd, Cgg), cut-off frequency (fT), and maximum oscillation frequency (fMAX). These parameters quantify the influence of parasitic capacitances on switching speed and the maximum useable frequency for analog and RF applications. Analyzing Cgs, Cgd, and Cgg reveals the impact of gate control on high-frequency operation. The device having 15 nm channel length, exhibits an increase of 47.29 % in fT and 68.97 % increase in fMAX compared to device having 20 nm channel length. The findings underscore the significance of channel length optimization in enhancing the Analog and RF performance of n-type Silicon-based Double Gate Junctionless Transistors.