Impact of usage conditions on solder joint fatigue life

Abstract

In flip chip microelectronic packages, solder bumps are used to connect the silicon die and package substrate for electrical functionality. However, due to the large mismatch of silicon and organic package in the coefficient of thermal expansion (CTE), the solder bumps undergo large viscoplastic deformation in temperature cycling test and in field operation. The viscoplastic damage accumulates cycle by cycle, which leads to the bump failure by fatigue cracking after hundreds or thousands of thermal cycles. Underfill plays a key role in solder joint fatigue lifetime. In addition to the effects of underfill modulus and CTE, the glass transition temperature, T g , is also critical. Solder deformation is very sensitive to underfill modulus, the viscoplastic work is much larger when the temperature is above T g than below T g . The underfill is usually chosen such that T g is compatible with the operation temperature of processors, since its overall integrity can be optimized in terms of solder joint fatigue, underfill delamination and copper/low-k cracking. However, in usage, the junction temperature T j could potentially overshoot T g several degrees for several minutes. This situation will compromise the load-sharing ability of the underfill to protect the solder joints. The fatigue life of solder could be significantly impacted. In this paper, the effects of overshoot duration and the ramp rate are studied by modeling/simulation for both temperature cycling and power cycling tests, and compared with normal setpoint condition. Then, the field lifetime of solder joints is projected based on the simulation and the temperature cycling qualification test.