Chip scale package (CSP) solder joint reliability and modeling

Abstract

A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behaviour of the solder joints in chip scale packages (CSP) mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. Finite element models, incorporating the viscoplastic flow and evolution equations, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless lead-on-chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints, while a dwell time in excess of 10 minutes per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated, and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.