Impact of TSV bump and redistribution layer on crosstalk delay and power loss

Abstract

The performance of a 3D IC is primarily reliant on the selection of an appropriate bump shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress, power loss and crosstalk issues. TSV bump with a tapered structure have recently attracted considerable attention owing to its low volume fraction and coupling capacitance, that can substantially reduce the stress and crosstalk concerns. An impact of the redistribution layer (RDL), intermetal dielectric and high frequency skin effect are appropriately taken into account for the tapered TSV (T-TSV) with a cylindrical, barrel and tapered bump shape. A mathematical framework of the resistance–inductance–conductance–capacitance (RLGC) structure of the proposed T-TSV have been formulated by effectively considering the coupling, passivation and fringing capacitance of the RDL. In order to benchmark the proposed electrical equivalent circuit, the structural model of the T-TSV is validated against the fabrication based experimental results, and a subsequent analysis have been performed for the stress, crosstalk induced delay, and power loss. The proposed TSV structure is in good agreement with the experimental results with an average deviation of only 2.8%. Furthermore, irrespective of bump height, the tapered bump based T-TSV can effectively reduce the overall crosstalk induced delay, stress, power delay product (PDP), insertion and reflection losses with an average deviation of 20.22%, 22.30%, 23.55%, 8.01%, and 10.32%, respectively, when compared to the barrel and cylindrical bumps. In addition, it has been observed that the overall rate of change in PDP, power losses and crosstalk induced delay with considering RDL are 18.8%, 20.50%, and 25.22%, respectively independent of the bump shapes.