Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV

Abstract

The selection of a suitable bump shape is critical to the performance of a 3D packaging system. The most widely used bump shape (cylindrical) is facing significant reliability issues, including coefficient of thermal expansion (CTE) mismatch, stress and power loss. Bump with a tapered shape have procured a lot of attention recently because of their low volume fraction and coupling capacitance, which can significantly minimize stress and crosstalk related delay. In order to quantify the effective CTE and stress of different solder structures the bump/underfill composite assembly is quantitatively studied using 3D unit-cell technique, which takes evenly distributed bump in the underfill. The temperature-dependent effective CTE of the evenly distributed bump incorporating the volume fraction can be used for the analysis of the stress issues. Additionally, for the analysis of the power loss, the analytical π based impedance network is proposed. The model was successfully verified by EM simulation under the different frequency range. Furthermore, a distinctive electromagnetic (EM) based model is used to analyze the NEXT (Near end) and FEXT (Far end) crosstalk delay using coupled bump arrangement at 32 nm technology. Using Computer Simulation Microwave Studio (CST MWS) industry-standard EM simulations tool, the crosstalk induced delay is obtained upto 20 GHz operating frequencies for different bump architectures i.e. cylindrical, spherical and tapered. Considering a tapered bump, a substantial improvement in NEXT, FEXT, and CTE at 32 nm technology is observed as 3.39%, 4.02%, 7.03%, 8.08% 11.88%, and 40.18% respectively compared to the spherical and cylindrical bump.