Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications

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The need to enhance transistor performance below 22-nm node has brought in a change in transistor architecture from planar bulk to either ultrathin-body SOI (UTB SOI) or 3-D trigate transistors. Further improvement in transistor performance at sub-7-nm node is likely to require replacement of silicon channel with high-mobility compound semiconductor (III-V) materials. This paper presents a numerical 3-D simulation study of process variation and sidewall roughness/surface roughness effects on 3-D trigate (tapered and rectangular cross sections) on bulk and UTB SOI devices. We also investigate the effects of variation on future III-V trigate transistors using the same 3-D TCAD scheme. The results show that the threshold voltage variation value, ΔVT, in rectangular Si trigate and UTB SOI due to all the variation sources are 13.1 and 24.6 mV, respectively. Moreover, between Si and III-V compound semiconductors, the In0.53Ga0.47As trigate shows 1.5 times lower total ΔVT value making it a promising candidate for Si replacement. A Monte Carlo study of 6T SRAM cell with fin width or body thickness variation show that the 3σ value of read static noise margin [3σ (RSNM)] is least in SRAMs with rectangular Si trigate. This paper also shows that a 6T SRAM cell at different VCC shows that a Si trigate has VCCmin below 0.4 V.