Impact of the substrate and buffer design on the performance of GaN on Si power HEMTs

Abstract

This paper presents an extensive analysis of the impact of substrate and buffer properties on the performance and breakdown voltage of E-mode power HEMTs. We investigated the impact of buffer thickness, substrate resistivity and substrate miscut angle, by characterizing several wafers by means of DC and pulsed measurement.The results demonstrate that: (i) the resistivity of the silicon substrate strongly impacts on the breakdown voltage and vertical leakage current. In fact, highly resistive substrates may partly deplete under high vertical bias, thus limiting the total potential drop on the epitaxial layers. As a consequence, the vertical IV plots show a “plateau”, that limits the vertical leakage. (ii) the depletion of the substrate may worsen the dynamic performance of the devices, due to an enhancement of buffer trapping. (iii) Larger buffer thickness results in an increased robustness of the vertical stack, due to the thicker insulating region. (iv) the miscut angle (0°, 0.5°, and 1°) can significantly impact on both threshold voltage and the 2DEG density; devices with miscut substrate have higher current density. On the other hand, the dynamic on-resistance variation is comparable in the three cases.