Impact of Strained-Si Channel on Complementary Metal Oxide Semiconductor Circuit Performance under the Sub-100 nm Regime

Abstract

The impact of the enhanced mobility of a strained-Si channel on the performance of sub-100 nm complementary metal oxide semiconductor (CMOS) circuits is investigated by the combination of device and circuit simulations, considering both velocity saturation and velocity overshoot effects. It is found that higher mobilities of strained Si become more advantageous with reducing the channel length. It is also pointed out that the increase in energy relaxation time in strained Si, in addition to higher mobility, is effective for the enhancement of the circuit performance. The evaluated performance of 50 nm strained-Si CMOS amounts to around 1.7 times that of bulk-Si CMOS.