Impact of strain and DP position on the performance of Vertical Strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Abstract

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The strain is induced in the structure by varying the mole fraction of Silicon Germanium layer as well as the channel thickness. Increase in mole fraction at the interface of channel region results in increase in strain in the channel. In order to maintain strain in the channel region, a relaxed Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1−x</inf> Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> layer is required. S value for DP place at source side is higher (S=24.4 mV/decade) as compared at the drain side (S=18.9 mV/decade) intrinsic region. The impact ionization rate depends on the electric field at drain side intrinsic zone. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. Due to the DP layer, improve stability of threshold voltage, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> and subthreshold slope, S was found for VESIMOS-DP device of various size ranging from 20nm to 80nm which justified the vicinity of DP on improving the performance of the device