Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Abstract

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (dp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.