Impact of strained SiGe on the performance of Vertical Strained SiGe Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP)

Abstract

The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. Strain engineering has been applied as an attempt to improve VESIMOS-DP performance. The device was examined by varying the amount of Ge in the strain and the strained layer thickness. A thin layer of strained SiGe with Ge concentration of 30% is placed inside the device. This Ge concentration will be varied from 10%-50% in this paper. The increase in strain caused an increase in electron mobility and lowered the threshold voltages further. This can be attributed to the bandgap reduction that arises due to the increased amount of strain in the strained SiGe layer. However, such a thin layer still suffers severely from alloy scattering although being reduced significantly by the presence of DP layer. Therefore, an optimum mole fraction and thickness of the strain layer is chosen to reduce the high supply voltage without affecting the device performance. Due to DP layer, improve stability of threshold voltage and subthreshold slope was found for VESIMOS-DP device of various size ranging from 20nm to 80nm which justified the vicinity of DP on improving the performance of the device.