Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks

Abstract

In this work, we discuss how the position of the flat band voltage with respect to the starting voltage of the C-V measurement sweep can influence the estimation of the hysteresis in high-k/InGaAs MOS devices. We show that, with the support of experimental data and conceptual oxide defect band calculations, the interpretation and subsequent parameter extraction from flat-band voltage shifts observed in III-V MOS devices is more complex as compared to Si gate stacks. It is demonstrated that such complication arises due to the wider distribution of defect levels in the dielectric band gap in the case of InGaAs/high-k stack as compared to standard Si/SiO2/HfO2 MOS. In particular, for Al2O3 deposited on InGaAs, two wide, partially overlapping oxide defect bands are identified, centered ∼1.5 eV and ∼0.5 eV above and below the channel conduction band, respectively. Such defect levels are expected to affect the device operation and reliability.