Impact of Defect Engineering on High‐Power Devices

Abstract

Processing of electrical power at megawatt to gigawatt level in the industry, traction, and transmission and distribution requires high‐power devices with a blocking capability up to 10 kV. The mainstream ones require high‐purity silicon wafers with the lowest possible defect content (contamination) and maximal homogeneity of resistivity and thickness. To satisfy current ratings in a typical range of 1–6 kA, single diode or thyristor may occupy nearly the whole 100–150 mm silicon wafer. In addition to the doping profile optimization and gettering in the front‐end processes, the devices are subject to defect engineering to adjust uniformly or locally the recombination lifetime of carriers. In insulated gate bipolar transistors (IGBTs), it is also about dopant activation below 500 °C. Satisfaction of all extremal demands laid on those devices is not possible without the knowledge developed by defect engineering community in the past decades. Some relevant industrial examples of screening the contamination in typical production of silicon high‐power devices are demonstrated as well as the advanced defect engineering methods for increasing device functionality and power density.