Abstract
The ever-increasing demand for portable electronic devices has led to the downscaling of metal oxide semiconductor (MOS) field effect transistors (FETs). However, the downscaling of MOSFET beyond nanometer regime have been stuck by the presence of lethal short channel effects. These effects include velocity saturation, drain induced barrier lowering (DIBL), and quantum confinements etc. To overcome these effects researchers have introduced the double-gate (DG) MOSFET. However, the formation of abrupt junction at deep technology nodes is another constraint to downscaling of MOSFETs. To get rid of this problem, junctionless (JL) MOSFET comes into picture that have all the regions (source, channel, and drain) uniformly doped. Moreover, from digital IC point of view, logic gates are the basic building blocks. Also, the performance analysis of logic gates is an essential requirement to understand the performance of JL-DG-MOSFET for digital ICs. Subsequently, this paper presents the effect of JL-DG-MOSFET on the performance of fundamental logic gates like NOT, NAND, and NOR gate.
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