Impact of Channel Hot Carrier Effect in Junction-and Doping-Free Devices and Circuits

Abstract

In this brief, we have investigated the time-dependent performance degradation of digital benchmark circuits due to channel hot carrier (CHC) stress in junction-and doping-free devices. For device–circuit interaction, we have developed the lookup table-based Verilog-A models of both devices for circuit simulations. At device level, the drain current of conventional n-type junctionless FET (JLFET) is degraded by 20%–25%; however, dopingless JLFET experiences 10%–15% degradation in drain current due to CHC stress of different time spans. The circuit-level simulations of digital benchmark circuits, such as standard six-transistor static random access memory (SRAM) cell and ring oscillator (RO), have large impact of CHC stress. For example, operating frequency of RO designed with conventional JLFET is degraded by 3.3 to 5 times due to CHC stress of 2000 and 6000 s. Similarly, read and write delays of SRAM cell are also degraded by CHC stress conditions.